Pinned Repositories
ahaHLS
An open source high level synthesis (HLS) tool built on top of LLVM
ahblite_mem
apb_vip
Verification IP for APB protocol
awesome-cpus
All CPU and MCU documentation in one place
awesome-hdl
Hardware Description Languages
msk
my_uvm_3ch
my_uvm_ahb2
my_uvm_demo
my_uvm_demo
uvm_ref_flow_1.1
uvm_ref_flow_1.1
hao310rui140326's Repositories
hao310rui140326/AXI_spec_chinese
AXI协议规范中文翻译版
hao310rui140326/basic_verilog
Must-have verilog systemverilog modules
hao310rui140326/CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
hao310rui140326/chisel-book
Digital Design with Chisel
hao310rui140326/chisel3
Chisel 3: A Modern Hardware Design Language
hao310rui140326/Coyote
Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.
hao310rui140326/DeepLearningSystem
Deep Learning System core principles introduction.
hao310rui140326/FEC
FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
hao310rui140326/FEC-Archive-Verilog
Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward Error Correction coders and decoders Hamming code, Golay code (24), 4-dimension 8-ary phase shift keying trellis coded modulation (TCM_4D_8PSK), BCH, CCSDS and recursive systematic convolutional (RSC) Turbo codes
hao310rui140326/fpga-drive-aximm-pcie
Example designs for FPGA Drive FMC
hao310rui140326/gemmini
Berkeley's Spatial Array Generator
hao310rui140326/hls4ml
Machine learning on FPGAs using HLS
hao310rui140326/litepcie
Small footprint and configurable PCIe core
hao310rui140326/litex
Build your hardware, easily!
hao310rui140326/Neural-Networks-on-Silicon
This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.
hao310rui140326/oh
Verilog library for ASIC and FPGA designers
hao310rui140326/OpenFPGA
An Open-source FPGA IP Generator
hao310rui140326/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
hao310rui140326/pp4fpgas
Parallel Programming for FPGAs -- An open-source high-level synthesis book
hao310rui140326/python-opengl
An open access book on Python, OpenGL and Scientific Visualization, Nicolas P. Rougier, 2018
hao310rui140326/riscv-dv
Random instruction generator for RISC-V processor verification
hao310rui140326/soDLA
Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
hao310rui140326/spi-to-axi-bridge
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
hao310rui140326/ventus-gpgpu
GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
hao310rui140326/vericert
A formally verified high-level synthesis tool based on CompCert and written in Coq.
hao310rui140326/verilog-ethernet
Verilog Ethernet components for FPGA implementation
hao310rui140326/ViT
Implementing Vi(sion)T(transformer)
hao310rui140326/vit-pytorch
Implementation of Vision Transformer, a simple way to achieve SOTA in vision classification with only a single transformer encoder, in Pytorch
hao310rui140326/ZAP
ZAP is a High Performance ARM(R) V5TE Compatible Superpipelined Processor with Caches, MMUs and TLBs that is capable of reaching 143MHz@Artix-7 FPGA. ZAP is Copyright (C) 2016-2022 Revanth Kamaraj. Released under the GNU GPL v2 license.
hao310rui140326/zju-icicles
浙江大学课程攻略共享计划