hao310rui140326

hao310rui140326's Stars

• hpcaitech/ColossalAI

  Making large AI models cheaper, faster and more accessible

  Language:Python38.7k3831.7k4.3k

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3.1k167176748

• enjoy-digital/litex

  Build your hardware, easily!

  Language:C2.9k97814556

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.2k115163687

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.4k5271438

• ZipCPU/zipcpu

  A small, light weight, RISC CPU soft core

  Language:Verilog1.3k6028153

• aolofsson/oh

  Verilog library for ASIC and FPGA designers

  Language:Verilog1.2k9935285

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1.1k39119256

• lnis-uofu/OpenFPGA

  An Open-source FPGA IP Generator

  Language:Verilog82043442160

• rougier/python-opengl

  An open access book on Python, OpenGL and Scientific Visualization, Nicolas P. Rougier, 2018

  Language:HTML6222636100

• seldridge/verilog

  Repository for basic (and not so basic) Verilog blocks with high re-use potential

  Language:Verilog547533139

• enjoy-digital/litepcie

  Small footprint and configurable PCIe core

  Language:Python4662868116

• spcl/gemm_hls

  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

  Language:C++297172951

• ZipCPU/wbuart32

  A simple, basic, formally verified UART controller

  Language:Verilog27616347

• ZipCPU/dblclockfft

  A configurable C++ generator of pipelined Verilog FFT cores

  Language:C++216141328

• fpgadeveloper/fpga-drive-aximm-pcie

  Example designs for FPGA Drive FMC

  Language:Tcl211312198

• fpgasystems/Coyote

  Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.

  Language:SystemVerilog209103863

• ZipCPU/autofpga

  A utility for Composing FPGA designs from Peripherals

  Language:C++16718419

• ZipCPU/openarty

  An Open Source configuration of the Arty platform

  Language:Verilog12014324

• dpretet/axi-crossbar

  An AXI4 crossbar implementation in SystemVerilog

  Language:SystemVerilog11531425

• cjhonlyone/picorv32_Xilinx

  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

  Language:Verilog664319

• fpgasystems/davos

  Distributed Accelerator OS

  Language:SystemVerilog5910828

• Lcrypto/FEC-Archive-Verilog

  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward Error Correction coders and decoders Hamming code, Golay code (24), 4-dimension 8-ary phase shift keying trellis coded modulation (TCM_4D_8PSK), BCH, CCSDS and recursive systematic convolutional (RSC) Turbo codes

  Language:Verilog524012

• ultraembedded/core_dbg_bridge

  UART -> AXI Bridge

  Language:Verilog525017

• UofT-HPRC/fpga-bpf

  A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark

  Language:Verilog4310012

• avl-bsuir/rv64x-base

  Open source GPU extension for RISC-V

  Language:Dockerfile40205

• williamyang4978/PipeCNN_Winograd

  An OpenCL-Based FPGA Accelerator for Compressed YOLOv2

  Language:C++36368

• delbel/bchverilog

  MATLAB script for generating unrolled shortened systematic BCH codecs for arbitrary k and t in Verilog

  Language:MATLAB7100

• olofk/zipcpu

  A small, light weight, RISC CPU soft core

  Language:Verilog210

• ypyp3/uart-axi

  AXI4 bus master, controlled by UART

  Language:SystemVerilog22