harshithaya's Stars
RGD2/icestorm_example
A very brief example / starter project for cliffordwolf/icestorm Open source FPGA tools. Works for both the iCEStick and the iCE40-HX8K Breakout Board
ChandrikaPattnaik/Universal-Synchronous-Receiver-Transmitter-USRT-
USRT represents Universal Synchronous Reciever Transmitter where the Reciever and Transmitter run synchronously, that is with the same frequency without any delay. When the 8 bit data is loaded to the Transmitter the NINTO interrupt goes high indicating that the Transmitter is busy loading the data and transmitting it serially through the SO output. The data transmitted through SO gets into the Reciever through SI input serially. When the serial loading occures in the Reciever, the Reciever Interrupt NINTI goes high. Once the serial feeding of data is complete NINTI goes low. Similarly, once the Transmitter finishes sending all the data to the Reciever, NINTO goes low. To know the starting of a data bit the SO line goes from 1 to 0 (High to Low).
kunalg123/vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
ayushc13/Implementation-of-Brick-Smasher-game-using-HDL-verilog-on-FPGA
A virtual/video game is simulation of a real world sport/game or a scenario, traditionally implemented on a digital systems such as a computer or a dedicated hardware gaming console, generally using traditional sequential programming languages, mainly C/C++. In this project we implement the electronic BRICK SMASHER game which is based on real world BRICK SMASHER game on FPGA (Field Programmable Gate Array) using Verilog HDL. Implementation in HDL (Hardware Description Language) is quite different from Implementation in sequential languages mainly because of the parallel nature of the HDLs, where sequential language code is executed by a digital core step by step, HDL code describes the functioning of a digital hardware, it is taken by synthesis tools that try to find a digital hardware implementation of the description, thus there is no step by step execution of the statement of HDL, and each statement is a smaller circuit in itself. The system is implemented on FPGA, which are modern programmable logic devices, i.e. we can program almost any digital function in it. Newer FPGA are capable of holding complete systems on them. They are called field programmable as they can be reprogrammed after manufacturing when they are in the field. They are sometimes called ‘sea of gates’, as that is what they exactly are, they consist of millions CLB (Complex Logic Blocks) arranged in a matrix interconnected by a network of programmable fuses. Each CLB is capable of implementing 3-4 input logic functions through LUTs (Look-up Table) and Flip Flops, exact capabilities of the CLBs depend on the Architecture of particular FPGA family.
jcchen305/Verilog-Sorting-Machine
pConst/basic_verilog
Must-have verilog systemverilog modules
sifive/freedom
Source files for SiFive's Freedom platforms
olofk/fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
ucb-bar/chisel-tutorial
chisel tutorial exercises and answers
hossamfadeel/256-Point_Parallel_FFT_DIF
cookacounty/open-skill
Open source SKILL code for Cadence Virtuso
teresalgarra/TSIU03
The four labs for TSIU03 System Design kurs in Linköping University (teacher: Mario Garrido Gálvez).
tuna/thuthesis
LaTeX Thesis Template for Tsinghua University
matze/mtheme
A modern LaTeX Beamer theme
roo16kie/FFT_verilog
using verilog to implement Fast Fourier Transform
bharathk005/Verilog_projects
HDMI + GPU-pipeline + FFT
sabolfazlgh/R4MDC
16 point FFT (R4MDC)
adityasangawar2007/256-Point-FFT
The inputs are 20 bits of real, and 20 bits imaginary data. The binary point is 18 bits from the right. The inputs are ranged between -1 and +1. The interface has a start signal, with the first input data point. This is followed by 255 samples of complex data. An FFT and IFFT require a scaling factor. This is traditionally placed on the IFFT. This project places the scaling (/256) on the FFT output. This implies that the range of the output will also be between -1 and + The design calculation completes in 256 clocks to complete one FFT. The FFT has 8 layers of 128 butterfly operations. This is 1024 butterfly operations. To complete in time, there are 4 butterfly operations happening concurrently. Each butterfly operation requires a complex multiply. The complex multiply requires 4 actual multiplies. Design Limit - 4 butterfly operations of 4 multipliers each. The total design (outer level, and all included hierarchies) does not have more than 16 multiplies. The design synthesizes and runs at the gate level at 300 MHz. (3.3ns cycle time)
Wandmalfarbe/pandoc-latex-template
A pandoc LaTeX template to convert markdown files to PDF or LaTeX.
Wookai/paper-tips-and-tricks
Best practice and tips & tricks to write scientific papers in LaTeX, with figures generated in Python or Matlab.
HarisIqbal88/PlotNeuralNet
Latex code for making neural networks diagrams
harshithaya/projects
dattngo/Dynamic-FFT-Algorithm-Matlab
Recofiguration FFT Algorithm runs on matlab version in order to generate input data and cross check with VLSI architecture.
dattngo/Dynamic-MFCC-Architecture-Matlab
Matlab-based model is implemented initially to compare with VLSI architecture's results
posenhuang/deeplearningsourceseparation
Deep Recurrent Neural Networks for Source Separation
sjtug/SJTUThesis
上海交通大学 LaTeX 论文模板 | Shanghai Jiao Tong University LaTeX Thesis Template
luong-komorebi/Begin-Latex-in-minutes
📜 Brief Intro to LaTeX for beginners that helps you use LaTeX with ease.
ucb-bar/riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
jasonlin316/A-Single-Path-Delay-32-Point-FFT-Processor
A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.
fengyulin1996/Verilog-DSP
FIR，FFT based on Verilog