Issues
- 7
- 3
Allow Data Graphs to stay open after a sim ends.
#1199 opened - 1
VHDL "others" incompatibility
#1194 opened - 4
7474 entity Verilog export
#1193 opened - 0
LedMatrix on MacOS clips at bottom
#1191 opened - 2
Chaging the size of a custome components
#1190 opened - 2
Oscillation in Delay after EEPROM - bug?
#1188 opened - 0
- 0
macOS installer?
#1184 opened - 1
Associate .dig files with Digital in macOS
#1183 opened - 0
-
#1181 opened - 2
How do you scale down this gui?
#1180 opened - 4
Ram with multiple outputs
#1178 opened - 2
Option to export HDL files from CLI
#1177 opened - 3
Cannot analyze Node External
#1173 opened - 0
Installer for windows
#1172 opened - 3
Export to Verilog
#1171 opened - 2
Open .tru and .fsm from main window
#1167 opened - 4
Feedback circuits
#1166 opened - 5
Bug in the "counting probe"
#1164 opened - 2
- 6
Reduce components through configurable inputs
#1155 opened - 1
Sine IO?
#1153 opened - 1
- 1
Convert Logisim to Dig
#1148 opened - 2
RAM, Chip Select Multi bit High-Z
#1146 opened - 1
Exception when browsing savefile
#1142 opened - 4
Option to disable auto-incrementing labels
#1141 opened - 1
- 3
How to deal with custom n bit input?
#1138 opened - 4
SystemVerilog
#1133 opened - 2
Library Issue
#1132 opened - 2
Monospaced font for text boxes
#1129 opened - 2
Better/more highlighting for the Find function
#1128 opened - 1
Error when exporting 74LS245 to Verilog
#1124 opened - 1
- 2
Current state at Error
#1119 opened - 0
Documentation wrong for the RS-component
#1118 opened - 0
Allow changing the Telnet buffer size
#1114 opened - 17
Sub 1 hertz clock
#1113 opened - 0
Italian translation update
#1110 opened - 1
Making Digital standalone executable or app.
#1105 opened - 4
- 2
Exponentiation Operator?
#1094 opened - 4
Spanish translation update
#1093 opened - 2
French translation update
#1092 opened - 2
Chinese translation update
#1091 opened - 2
- 2
Request: Bargraph
#1086 opened - 1