hongshen424/mips-processor
A dual-issue superscalar pipelined MIPS architecture which includes a cache, a branch-target buffer and a multiplication coprocessor. Completed in ECE154B in Spring 2016 with my partner Tristan Seroff.
Verilog
A dual-issue superscalar pipelined MIPS architecture which includes a cache, a branch-target buffer and a multiplication coprocessor. Completed in ECE154B in Spring 2016 with my partner Tristan Seroff.
Verilog