hsc-latte/caravel-hs32core
Repo for Nov 2020 Skywater 120nm shuttle run containing our custom HS32 CPU 🚀. This contains our GDS + tape-out files and post-synthesis tests 🧪. The RTL design is in a submodule.
VerilogApache-2.0
Repo for Nov 2020 Skywater 120nm shuttle run containing our custom HS32 CPU 🚀. This contains our GDS + tape-out files and post-synthesis tests 🧪. The RTL design is in a submodule.
VerilogApache-2.0