hushunkui

Pinned Repositories

• 1000base-x

  1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)

  Language:Verilog00

• 100G-fpga-network-stack-core

  This repo contains the Limago code

  0100

• 10base_t_software_PHY

  Language:C00

• 1G_CML_OpenFlow

  OpenFlow switch for NetFPGA 1G CML

  Language:Verilog00

• 8-bits-RISC-CPU-Verilog

  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（**处理器）简单结构和Verilog实现。

  Language:Verilog0100

• adapter

  An FPGA-based NetTLP adapter

  Language:SystemVerilog00

• AES-FPGA

  AES加密解密算法的Verilog实现

  Language:Verilog00

• aes-over-pcie

  A VHDL implementation of 128 bit AES encryption with a PCIe interface.

  Language:VHDL0100

• aes_netfpga10g

  Design and implementation of the AES crypto authentication module based on NetFPGA10G card

  Language:C00

• kc705-pcie-dma-gen2

  kc705-pcie-dma-gen2

  Language:Verilog10

hushunkui's Repositories