UP3 Tigerlake Based Circuit Board: CRC For DIMM Fails. So Fast Boot Never Occurs!

Question

UP3 Tigerlake Based Circuit Board: CRC For DIMM Fails. So Fast Boot Never Occurs!

Opened this issue 8 months ago · 14 comments

Hi. From the forum at the link above, we were redirected here. We have mentioned further details below:

Please check the attached log for the messages surrounding the text below.
[debug2.log] (https://github.com/intel/FSP/files/14163336/debug2.log)

MRC task -- Fast boot permitted -- Started.
Channel 0 Dimm 0 DimmCrc C97Eh, DimmSave->Crc C97Eh
Channel 0 Dimm 1 DimmCrc C97Eh, DimmSave->Crc 0h
Dimm has changed, cold boot required
MRC task Fast boot permitted -- FAILED, Status = 18h.

MRC Fast Boot is failing because of this. So the saved memory training results are never used after the 1st boot. Instead, cold boot
keeps occurring on the 2nd boot, 3rd boot etc.

Does someone know why the CRC error occurs? How can we prevent the error & enable Fast Boot?

Thanks!

Answer 1 · 2024-02-07T09:57:04.000Z

Good afternoon. I'm Josh and I was made aware of your issue. I need to confirm some of your board details:

What TGL-UP3 stepping are you using?
What reference board did you based your custom board?
I saw from the logs that you are using LPDDR4 16GB Soldered/Memory Down. Can you give me the brand and other details?
I have attached my debug log from my reference board. The main difference other than the memory size is that there is a mismatch on the CRC on Channel 0 Dimm 1.

You can take a look and compare our debug logs. I will check further on what is the possible problem.

With best regards,
Josh

putty_tglup3_20240208005856.log

Answer 2 · 2024-02-07T11:43:20.000Z

Hi Josh.

We use stepping 1.
We used the RVP reference board. LPDDR4 Memory routing is based on "609182_TigerLake_UP3_TGL_UP3_LPDDR4x_AEP_TDK_Rev1p0". Rest of the platform is based on "612304_TGL_UP3_LPDDR4x_RVP_TDK_Rev1p0"
The LPDDR part no. is MT53D1024M32D4 (from Micron).

Timing values can be configured through the Spd_Lpddr4.bin file in Slimbootloader. I've shared this file at the link below:
Spd_Lpddr4.bin

Thanks for your debug log. A question: How is the DIMM CRC calculated & for what purpose?

Thanks!

Answer 3 · 2024-02-08T03:47:42.000Z

Hi SShvish.

You are referring to the B1 Stepping, correct?

From what I know, the CRC16 is needed to detect a change in the DIMM module. Since your board is memory down, this is not possible.

The data from your log showed that a CRC is generated but the stored CRC from the previous Cold Boot is 0. That is the reason why it always does a Cold Boot.

It will take some time for me to root cause this, but I need to double confirm with you. Are you able to utilize or see the full 16GB main memory? In EFI Shell or OS?

With best regards,
Josh

Answer 4 · 2024-02-08T06:22:15.000Z

Hi Josh.

Here is some information from different lines in the debug log:

PCH Stepping : B0

TigerLake ULT: Stepping B0

CpuStepping: 1h

Yes. We are able to see the full 16 GB of memory in the OS.

Thanks!

Answer 5 · 2024-02-08T11:44:42.000Z

Also, from a photo of the processor:

CPU Spec Code: SRK0Y

Stepping: B1

Thanks!

Answer 6 · 2024-02-13T13:21:19.000Z

Hi Josh, Were you able to progress towards root-cause? Thanks!

Answer 7 · 2024-02-15T11:13:31.000Z

Hi SShvish,

Good evening. Sorry, I just returned from the long holiday. This is still in progress.

With best regards,
Josh

Answer 8 · 2024-02-16T08:45:36.000Z

Hi SShvish,

Good afternoon. Can you send an IPS ticket regarding this issue? I will take ownership of the ticket once it is posted.

With best regards,
Josh

Answer 9 · 2024-02-16T11:15:39.000Z

Hi Josh.

We don't have IPS privilege. How can we obtain it?

Thanks.

Answer 10 · 2024-02-16T11:33:27.000Z

Hi SShvish,

Normally, your Intel representative (PAE) will be the one to give you access to IPS as an NDA partner. He/She is the one who provided the reference documents you mentioned earlier. Are you able to contact this person?

I will reply on your original thread for someone who can assist on the IPS access.

Regarding the progress... I might have found a fix, but I am unsure yet as we have different memory configuration.

With best regards,
Josh

Answer 11 · 2024-02-17T02:18:53.000Z

Hi SShvish,

Good morning. I have responded in your original thread. Please contact your local FAE regarding IPS access.

With best regards,
Josh

Answer 12 · 2024-02-17T13:37:36.000Z

Hi Josh. Sorry for the delay: Actually, my company works till 7 PM on weekdays, but not on Saturday & Sunday!

I noticed your post, thanks a lot. I will get back to you on the coming Monday!

Answer 13 · 2024-03-13T07:07:05.000Z

Hi Josh,

I got the ability to make a new IPS case (with the Tigerlake product) only now. Sorry for the delay!

The IPS Case Number is 00868720.

Hope you can help us now. Thanks!

Answer 14 · 2024-03-14T03:32:23.000Z

Hi Siddhartha,

Good morning. That is great! I just took ownership. Our succeeding communique will proceed from there.

With best regards,
Josh