Pinned Repositories
A-convolution-kernel-implemented-by-Vivado-HLS
This project implements a convolution kernel based on vivado HLS on zcu104
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
Accelerating-CNN-with-FPGA
This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
AI-Chip
A list of ICs and IPs for AI, Machine Learning and Deep Learning.
AIChip_Paper_List
aimet
AIMET is a library that provides advanced quantization and compression techniques for trained neural network models.
albumentations
Fast image augmentation library and an easy-to-use wrapper around other libraries. Documentation: https://albumentations.ai/docs/ Paper about the library: https://www.mdpi.com/2078-2489/11/2/125
Awesome-Embedded
A curated list of awesome embedded programming.
awesome-emdl
Embedded and mobile deep learning research resources
awesome-fpga-list
A collection of some awesome public FPGA projects.
jaemyungkim's Repositories
jaemyungkim/awesome-fpga-list
A collection of some awesome public FPGA projects.
jaemyungkim/AI-Chip
A list of ICs and IPs for AI, Machine Learning and Deep Learning.
jaemyungkim/awesome-yolo-object-detection
🚀🚀🚀 A collection of some awesome public YOLO object detection series projects.
jaemyungkim/BJUT_Tutorials
Things to learn for new students in the Lab for AI chips and systems of BJTU .
jaemyungkim/CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
jaemyungkim/CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
jaemyungkim/data-gradients
Computer Vision dataset analysis
jaemyungkim/dnn-engine
AXI-Stream Universal DNN Engine with Novel Dataflow enabling 70.7 Gops/mm2 on TSMC 65nm GP for 8-bit VGG16
jaemyungkim/DNN_HLS_Accelerator
This repository contains source code for CNN layers of ALexNet using Xilinx HLS Vivado.
jaemyungkim/EfficientPyTorch
A PyTorch Framework for Efficient Pruning and Quantization for specialized accelerators.
jaemyungkim/finn
Dataflow compiler for QNN inference on FPGAs
jaemyungkim/finn-hlslib
Vivado HLS library for FINN
jaemyungkim/HandyFigure
HandyFigure provides the sources file (ususally PPT files) for paper figures
jaemyungkim/HLS-Tiny-Tutorials
jaemyungkim/LilNetX
Official PyTorch implementation of LilNetX: Lightweight Networks with EXtreme Model Compression and Structured Sparsification
jaemyungkim/micronet
micronet, a model compression and deploy lib. compression: 1、quantization: quantization-aware-training(QAT), High-Bit(>2b)(DoReFa/Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference)、Low-Bit(≤2b)/Ternary and Binary(TWN/BNN/XNOR-Net); post-training-quantization(PTQ), 8-bit(tensorrt); 2、 pruning: normal、regular and group convolutional channel pruning; 3、 group convolution structure; 4、batch-normalization fuse for quantization. deploy: tensorrt, fp32/fp16/int8(ptq-calibration)、op-adapt(upsample)、dynamic_shape
jaemyungkim/nanodet
⚡Super fast and lightweight anchor-free object detection model. 🔥Only 1.8MB and run 97FPS on cellphone🔥
jaemyungkim/Neural-Networks-on-Silicon
This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.
jaemyungkim/nni
An open source AutoML toolkit for automate machine learning lifecycle, including feature engineering, neural architecture search, model compression and hyper-parameter tuning.
jaemyungkim/numerical-linear-algebra
Free online textbook of Jupyter notebooks for fast.ai Computational Linear Algebra course
jaemyungkim/openhls
PyTorch model to RTL flow for low latency inference
jaemyungkim/pp4fpgas
Parallel Programming for FPGAs -- An open-source high-level synthesis book
jaemyungkim/repo
ZedBoard FPGA based Convolutional Neural Network (CNN) accelerator
jaemyungkim/RepVGG
RepVGG: Making VGG-style ConvNets Great Again
jaemyungkim/satay
jaemyungkim/Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
jaemyungkim/Tiny-YOLO-LSQ
This is an implementation of YOLO using LSQ network quantization method.
jaemyungkim/Vitis-AI
Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
jaemyungkim/Vitis_Embedded_Platform_Source
jaemyungkim/yolov2_xilinx_fpga
A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard