All digital implementation of classic analog mixed signal VLSI blocks like PLL and TRNG.
This section provides some analog PLL information for comparison with digital PLL implementations.
- John G. Maneatis Why Synthesizable-digital PLLs Are No Substitute for Hardened Mixed-signal PLLs
- OT3122t130 PLL for TSMC 130nm
- Adrian Freed A Synthesizable Hybrid VCO using Standard-Cell Multiplexers
- Saichandrateja Radhapuram,Takuya Yoshihara andToshimasa Matsuoka Design and Emulation of All-Digital Phase-Locked Loop on FPGA
- O V Shumkin, V A Butuzov, D D Normanov and P Yu Ivanov A low jitter all – digital phase – locked loop in 180 nm CMOS technology
- Akila Gothandaraman Design and Implementation of an All Digital Phase Locked Loop using a Pulse Output Direct Digital Frequency Synthesizer
- Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, and Kartikeya Mayaram A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy
- P.E. Allen LECTURE 080 – ALL DIGITAL PHASE LOCK LOOPS (ADPLL)
- Bo Jiang A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration
- Kusum Lata and Manoj Kumar ALL Digital Phase-Locked Loop (ADPLL): A Survey
- Kaiyuan Yang, David Blaauw, Dennis Sylvester A Robust -40 to 120°C All-Digital True Random Number Generator in 40nm CMOS
- V. Rajesh Pamula, Xun Sun, Sung Kim, Fahim ur Rahman, Baosen Zhang, and Visvesh S. Sathe An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 Mb/s, 2.58 pJ/bit in 65-nm CMOS
- Ihor Vasyltsov, Eduard Hambardzumyan, Young-Sik Kim, and Bohdan Karpinskyy Fast Digital TRNG Based on Metastable Ring Oscillator alternate
- Sha Tao and Elena Dubrova TVL-TRNG: Sub-microwatt True Random Number Generator Exploiting Metastability in Ternary Valued Latches
- opentitan