Valid signal of line buffer when last level is not a register

[norabarlow]

When the last level of a line buffer is not a register (such as in multichannel convolution), there are multiple valid signals connected to self.valid:

Error Validating def
ERROR: Cannot connect multiple outputs to an inputs
In Module: DesignTop
  self.valid : BitIn <== ub_hw_input_stencil_update_streamlinebuffer_bank_0_1.valid
  self.valid : BitIn <== ub_hw_input_stencil_update_streamlinebuffer_bank_0_0_1.valid
  self.valid : BitIn <== ub_hw_input_stencil_update_streamlinebuffer_bank_0_1_1.valid
  self.valid : BitIn <== ub_hw_input_stencil_update_streamlinebuffer_bank_0_2_1.valid
  self.valid : BitIn <== ub_kernel_streamlinebuffer_bank_0_1.valid
  self.valid : BitIn <== ub_kernel_streamlinebuffer_bank_0_0_1.valid
  self.valid : BitIn <== ub_kernel_streamlinebuffer_bank_0_1_1.valid
  self.valid : BitIn <== ub_kernel_streamlinebuffer_bank_0_2_1.valid

Example is from 16x16x32 3x3 convolution.

[joyliu37]

This problem related to the update of valid signal. I think our updated version of unified buffer functional model is different from the memory tile. @mbstrange2 Max do you think you need some unit test scripts for implementing this new feature.

[mbstrange2]

I'm going to need more information on this. I need an explanation of what changed and what you need in hardware to reflect this.

[mbstrange2]

StanfordAHA/garnet#379