Welcome to the Digital System Design with Verilog repository! Here you'll find a collection of Verilog files used for digital system design labs.
This repository contains Verilog files covering a wide range of digital system design components and concepts, including:
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Flip-flops: Files such as D_FF.v, JK_ff.v, SR_Flipflop.v, T_FF.v, etc., representing different types of flip-flops.
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Gates: Verilog files like and_gate.v, or_gate.v, xor_gate.v, not_gate.v, etc., demonstrating basic logic gates.
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Multiplexers and Demultiplexers: Files like multiplexer.cr.mti, demultiplexer1_4.v, decoder5to32_2to4.v, etc., showcasing multiplexing and demultiplexing operations.
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Adders and Substractors: Files like addsub.cr.mti, fa_data.v, and multi_gate.v, illustrating arithmetic operations.
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Behavioral Models: Verilog files like behavior.cr.mti, gatelevel.cr.mti, flipflops.cr.mti, etc., providing behavioral models for different digital components.
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Dataflow Models: Files like dataflow.cr.mti, fs_data.v, hs_data.v, etc., representing dataflow models for digital systems.
To get started, clone or download this repository to your local machine. Open the Verilog files in your preferred HDL simulator or editor to explore the digital system designs.
Each Verilog file is named according to the component or concept it represents. Open the files to view the Verilog code and use them as references for understanding digital system design principles. You can simulate these designs using HDL simulators to observe their behavior.
Contributions to this repository, such as additional Verilog files or improvements to existing ones, are welcome! Feel free to open a pull request.
This repository is licensed under the Apache 2.0 License.