About cache problems when write data in memory-mapped mode

[sudashannon]

Hi koendv, thank you for your repo. It helps me to deal with the OSPI psram.
To solve the cache problems when write, I take the stm32's AN5050 for an example and it says:



So I change my OSPI configuration to:

And rerun the memtest without cache_invalidate and cache_clean operation, it succeed!

F.Y.I

[sudashannon]

Besides, I also change this region to MPU_ACCESS_NOT_BUFFERABLE.

[koendv]

On Sun, 01 Jan 2023 23:28:09 -0800 Leon Shan ***@***.***> wrote: Hi koendv, thank you for your repo. It helps me to deal with the OSPI psram. To solve the cache problems when write, I take the stm32's AN5050 for an example and it says:    So I change my OSPI configuration to:  And rerun the memtest without cache_invalidate and cache_clean operation, it succeed!   F.Y.I

This is very good news. I think this means large, cheap memory for micropython. I have some questions. What spi ram chip you are using? What happens if you do not set MPU_ACCESS_NOT_BUFFERABLE? Can you open a Pull Request, with the changes you made and mentioning your name in README.md? best, koen

[sudashannon]

Hi koen:
These days I have been tested different ospi configuration and MPU configuration and come the conclusion that:

1. OSPI configuraion is not the key to solve the cache problems.
2. Aceess to memory-mapped memory will be valid only if the MPU is set to write-through or undefined, but when MPU is set to undefined, the memory-mapped memory will not support unaligned access:
   
   BRs
   Leon

[koendv]

On Tue, 10 Jan 2023 17:13:15 -0800 Leon Shan ***@***.***> wrote: Hi koen: These days I have been tested different ospi configuration and MPU configuration and come the conclusion that: 1. OSPI configuraion is not the key to solve the cache problems. 2. Aceess to memory-mapped memory will be valid only if the MPU is set to write-through or undefined, but when MPU is set to undefined, the memory-mapped memory will not support unaligned access:  BRs Leon

Hi Leon. At least the ospi ram can be used. Without cache memory access will be slower; I think memory access will be 8 times slower. But the cache problem may be solved in other processor models. A question: Does ospi ram memory work with micropython? If, in the linker script, you replace the line RAM (xrw) : ORIGIN = 0x20010000, LENGTH = 192K with RAM (xrw) : ORIGIN = 0x90000000, LENGTH = 8M /* spi ram */ does micropython work? If ospi memory works with micropython, then a way should be found for micropython to use both the ram inside the mcu, and the ospi ram. A possible solution would be to change malloc.c so small amounts of memory are taken from internal ram, big amounts of memory from ospi ram. And if everything works, then open a pull request so the new code becomes part of micropython? 你用中文写没问题。 best, koen

[koendv]

I wanted to say: 你用汉字写没问题。