Fails to compile

[darkstar007]

When running the makefile in ulx3s, it fails with:

End of script. Logfile hash: 770a9a0614, CPU: user 0.82s system 0.09s, MEM: 264.38 MB peak
Yosys 0.16+34 (git sha1 c3a3f68b4, clang 11.0.1-2 -fPIC -Os)
Time spent: 70% 55x read_verilog (0 sec), 6% 15x opt_clean (0 sec), ...
nextpnr-ecp5 --85k --package CABGA381 --freq 25 --textcfg  bin/toplevel.config --json bin/toplevel.json --lpf ulx3s_v20.lpf 
Warning: net 'clk25_mhz' does not exist in design, ignoring clock constraint
ERROR: IO 'locked' is unconstrained in LPF (override this error with --lpf-allow-unconstrained)
1 warning, 1 error
make: *** [ulx3s.mk:17: bin/toplevel.config] Error 255

To fix it I made this change:

diff --git a/ulx3s/ulx3s.mk b/ulx3s/ulx3s.mk
index 9db2192..6bc3af5 100644
--- a/ulx3s/ulx3s.mk
+++ b/ulx3s/ulx3s.mk
@@ -11,7 +11,7 @@ prog: $(BUILDDIR)/toplevel.bit
 
 $(BUILDDIR)/toplevel.json: $(VERILOG)
        mkdir -p $(BUILDDIR)
-       yosys -p "synth_ecp5 -json $@" $^
+       yosys -p "synth_ecp5 -top beeb -json $@" $^
 
 $(BUILDDIR)/%.config: $(PIN_DEF) $(BUILDDIR)/toplevel.json
         nextpnr-ecp5 --${DEVICE} --package CABGA381 --freq 25 --textcfg  $@ --json $(filter-out $<,$^) --lpf $< 

Thanks,
Matt

[lawrie]

Thanks for that. I have pushed the change. Several of my projects that I have not touched for a while have that issue.