lionheart117

lionheart117's Stars

• ccxt/ccxt

  A JavaScript / TypeScript / Python / C# / PHP cryptocurrency trading API with support for more than 100 bitcoin/altcoin exchanges

  Language:Python32.6k93410.2k7.5k

• mementum/backtrader

  Python Backtesting library for trading strategies

  Language:Python14.1k60903.9k

• vnotex/vnote

  A pleasant note-taking platform in native C++.

  Language:C++11.8k2362.2k1.2k

• FMInference/FlexGen

  Running large language models on a single GPU for throughput-oriented scenarios.

  Language:Python9.1k11181540

• aiboboxx/clashfree

  clash节点、免费clash节点、免费节点、免费梯子、clash科学上网、clash翻墙、clash订阅链接、clash for Windows、clash教程、免费公益节点、最新clash免费节点订阅地址、clash免费节点每日更新

  8.3k1340857

• adam-maj/tiny-gpu

  A minimal GPU design in Verilog to learn how GPUs work from the ground up

  Language:SystemVerilog7k6823521

• riscv/riscv-isa-manual

  RISC-V Instruction Set Manual

  Language:TeX3.6k206858624

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.2k911k675

• ucb-bar/chipyard

  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

  Language:Scala1.6k86659628

• lowRISC/ibex

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  Language:SystemVerilog1.3k96834523

• vortexgpgpu/vortex

  Language:Verilog1.2k39110252

• gpgpu-sim/gpgpu-sim_distribution

  GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.

  Language:C++1.1k46169505

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1.1k39119256

• VerticalResearchGroup/miaow

  An open source GPU based off of the AMD Southern Islands ISA.

  Language:Verilog1k14516237

• openhwgroup/cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  Language:SystemVerilog93482482412

• xuhaoyang/ClashForAndroid

  A rule-based tunnel for Android.

  Language:Kotlin8701104.5k

• ucb-bar/gemmini

  Berkeley's Spatial Array Generator

  Language:Scala78530182160

• HuobiRDCenter/huobi_Python

  Python SDK for Huobi Spot API

  Language:Python68037113332

• MikePopoloski/slang

  SystemVerilog compiler and language services

  Language:C++59429673132

• THU-DSP-LAB/ventus-gpgpu

  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

  Language:Scala592142570

• pulp-platform/ara

  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

  Language:C35622180126

• bobzhuyb/ns3-rdma

  NS3 simulator for RDMA over Converged Ethernet v2 (RoCEv2), including the implementation of DCQCN, TIMELY, PFC, ECN and shared buffer switch

  Language:Python2491142116

• schoeberl/chisel-examples

  Chisel examples and code snippets

  Language:Tcl22420978

• tukl-msd/DRAMSys

  DRAMSys a SystemC TLM-2.0 based DRAM simulator.

  Language:C++206164754

• IObundle/iob-cache

  Verilog Configurable Cache

  Language:Verilog16782632

• ZipCPU/eth10g

  10Gb Ethernet Switch

  Language:C15010118

• aignacio/ravenoc

  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

  Language:SystemVerilog13961432

• pulp-platform/FlooNoC

  A Fast, Low-Overhead On-chip Network

  Language:SystemVerilog12262219

• pulp-platform/axi_llc

  Language:SystemVerilog184615

• lionheart117/hzone

  Python SDK for Huobi Spot API

  Language:Python2000