lj-k's Stars
jiegec/kb
My knowledge base
veripool/verilog-mode
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
kaitoukito/Computer-Science-Textbooks
Collect some CS textbooks for learning.
Xilinx/libsystemctlm-soc
SystemC/TLM-2.0 Co-simulation framework
kaitoukito/Integrated-Circuit-Specifications
Collect some IC specs for learning.
riscv-software-src/riscv-isa-sim
Spike, a RISC-V ISA Simulator
remzi-arpacidusseau/ostep-typos
bespoke-silicon-group/basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
riscv/riscv-v-spec
Working draft of the proposed RISC-V V vector extension
pikeszfish/releaseTracker
track github repo release
riscv/riscv-crypto
RISC-V cryptography extensions standardisation work.
openhwgroup/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
cnrv/RISCV-East-Asia-Biweekly-Sync
Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.
ruanyf/weekly
科技爱好者周刊，每周五发布
XUANTIE-RV/riscv-aosp
Patches & Script for AOSP to run on Xuantie RISC-V CPU
geektutu/high-performance-go
high performance coding with golang（Go 语言高性能编程，Go 语言陷阱，Gotchas，Traps）
risclite/SuperScalar-RISCV-CPU
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
Tyrrrz/LightBulb
Reduces eye strain by adjusting screen gamma based on the current time
zadam/trilium
Build your personal knowledge base with Trilium Notes
satwikkansal/wtfpython
What the f*ck Python? 😱