TeensyDelay Interfering with PWM
nate266 opened this issue · 3 comments
When using the library, I noticed that the analogWrite() would not work on some of the ports. Specifically, whenever I included the TeensyDelay::begin() statement in my code, the pwm would not work on pins 5 and 6, but would still work on pin 4. However, I could still control the pins using digitalWrite(), just not analogWrite(). If I removed the TeensyDelay::begin(), all three pins could successfully output the correct PWM. I am using a Teensy 3.5.
When I quickly looked through the datasheet for these FTM timers, it appears that the PWM also utilizes these timers which could be the cause of the problems. I managed to solve the problem for now by changing to TIMER_FTM3, but I am worried that it could affect the PWM on other ports that I haven't tested yet.
Has anyone else noticed this problem? Any ideas on the best way to deal with it?
You are right, analogWrite() also uses the FTM/TPM timers. I just noticed that I didn't mention this in the readme. Sorry for that.
As you already found out, you can select the timer used by TeensyDelay in config.h to avoid/reduce clashes with analogWrite(). Here https://www.pjrc.com/teensy/td_pulse.html you find a list of which pin uses which timer for analogWrite() (scroll down to PWM Frequency).
Thanks for your reply. Do you know if there is an easy way to use timers from multiple FTM sets with the same library? For example, I have a few available timers on FTM0 and a few others on FTM3. I'd ideally like to be able to use some of each to implement various timer functions that I need. As far as I can tell this library currently requires you to pick a set in the config.h file.
That won't work. Each FTM has exactly one counter. Basically, the FTM channels are just separate register values to generate interrupts / DMA if the one and only counter reaches the stored channel value.
TeensyDelay reprograms the chosen FTM, so it will influence all channels of that FTM.
Don't know what you want to achieve but there are other counters in the system which could be utilized for generating delays.