m8pple/arch2-2016-cw

Exception behaviour

ps-george opened this issue · 1 comments

Do we increment the program counter or not?

If an exception or error occurs, the CPU and memory state
should be left unchanged. This is so that the user can
inspect what happened and find out what went wrong.

From this I assume not.

Agreed - you do not increment the program counter.

Imagine a user of the CPU has the following code:

while( mips_success == mips_cpu_step(hCPU) ) ;

The loop will break on the first failing instruction, but how could
the user know which instruction cause the problem? You could
argue that the caller could get the PC and subtract 4, but
what if the failing instruction is in the delay-slot of a taken-branch?

In pseudo-assembly:

mov 5, 0x7FFFFFFFul
j AFTER // Branch to jump
add 5, 6, 7 // Delay-slot for branch
sub ...

AFTER:
sub ...

The add instruction will cause an overflow, but if the PC is modified then
it will point to ether of the two sub instructions, depending what the
implementation does. If it is the second instruction, which would make
sense if the update looks like:

pc=pcNext;
pcNext=pcNext+4;

then how do you work out which instruction was the guilty one?