L1, L2, NOC_BW constraints not met

[madnan92]

Hi,

I am new to this tool and I ran run_example.sh and I noticed that in the hw file "acclerator_1.m" we specified cstr for L1, L2, NOC_BW and Offchip_BW.
But in the results.csv file, I can see NoC BW Req (Elements/cycle) | Offchip BW Req (Elements/cycle) | L2 SRAM Size Req (Bytes) | L1 SRAM Size Req (Bytes) which doesn't follow the constraints given in hw file.

Does it mean that maestro gives you the optimal numbers for these hardware specifications per layer?
If yes, then how are we evaluating given accelerator that we want to evaluate if evaluation is not conforming our hardware constraints?

Another question is regarding the definition of PE's in x-axis and y-axis.
If we want to evaluate exact eyeriss architecture with (12 x 14 PE's) how can we define that in hw file? I can see that we can provide total number of PE's.

I covered the tutorials and got the idea that cluster just takes a single parameter which shows the no of PE's in a single cluster.
In the run_example.sh mapping file what does the Cluster(64, P) means?
64 means 64 PE's in a single cluster. Does that infer that given 256 PE's total clusters available are 4?
What about P? what does that define?

Thanks.