New UII+ features focussed on C128(D)

Question

New UII+ features focussed on C128(D)

Opened this issue 5 years ago · 9 comments

Hi MarkusC64,

Would it be possible to get in contact to discuss some C128(D) specific features for the UII+

On one hand to discuss if you could take them on an implement into your fork of the release.
In that case I will add them to this 'issue' list individually.

Alternatively, if with your knowledge from the UII+ architecture you could provide guidance if they can be implemented at all in the UII+. Where we find others to do the leg work of coding and provide you with the code to add to your release.

Looking forward hearing from you, Would be great to receive a private message so our communications doesn't pollute your 'issues list'

Thanks in advance,

Answer 1 · 2019-09-27T01:56:18.000Z

I'm curious as to what kinds of things. Some things are likely not possible. But you could add your ideas to this thread.

Answer 2 · 2019-09-28T13:39:07.000Z

Hi Xlar54,

Thanks for responding, much appreciated!
Would be great if you can help out with making it reality.

The C128 Features I would like to discuss and see happening first would be at least;

Fast Serial for the IEC interface (C1571/1581 compatible).
Full support for .D71 /.D81 images.
C128 Kernel Replacement (like it is currently possible for the C64).
80 Column Menu support.

Would you have any comment on the feasibility/possibility of implementing these?
Looking forward to your reply.

Surely, when we get into the next phase I am happy to make all these individual feature requests with more descriptions.

Thanks in advance,

Answer 3 · 2019-09-28T14:05:24.000Z

Ad 4: I was told that this is impossible. Menu is done via DMA in Ultimax-Mode.
Ad 3: I do not think that is possible - after reading the MMU description.´of the C128.
Ad 2: xlar54 is working on d81 support voa the IEC device. We should test it before writing anything concerning d81 support.
Ad 1: Dunno if the SEQ line is wired to the FPGA in the U2(+).

Answer 4 · 2019-09-30T17:49:01.000Z

Hi Markus,

Thanks for your quick response.
Looking to your answers a few additional observations if that's ok;

Ad 4: I was told that this is impossible. Menu is done via DMA in Ultimax-Mode.
Why should this be an issue? Is there any reason to assume that the I/O block is not available in DMA mode? If the I/O isn't available wouldn't there be a way to enable the I/O block before going into the DMA mode. (Like the SuperCPU did in the past?)
As a side node I have loaded Ultimax Basic and was able to 'poke' characters on the 80colum screen. Surely, it is not the same but makes me wonder that if we do have the I/O block enabled we should be able to make it work right?

Ad 3: I do not think that is possible - after reading the MMU description.´of the C128.
Which items of the MMU description makes you think it doesn't allow for an external Kernel to be active instead of the internal one? (Hence, why is it possible for the C64)

Ad 2: xlar54 is working on d81 support voa the IEC device. We should test it before writing anything concerning d81 support.
Looking forward to this feature!

Ad 1: Dunno if the SEQ line is wired to the FPGA in the U2(+)
Within the VHDL of the UII+ there is the 'IEC_SRQ_IN : inout std_logic;' defined. So a reasonable assumption is that it should be available and working. But it can be validated of course.
Assuming it is available, are there any other requirements/dependencies to make the fast serial to work you know off?

Looking forward to your future reply,

Answer 5 · 2019-09-30T19:06:20.000Z

Ad 4: GideonZ/1541ultimate#31 (comment)
And yes, SuperCPU did this trick. But it needed an extra wire from the module to the inside of the C128. So it did some cheating.
Ad 3: Please read http://skoe.de/kernal/kernal-cartridge.pdf - there is nothing like that on the MMU for the kernal. You cannot simply set a signal on the expansion port bypassing the MMU. It's the point that expansion port signals have no influence - GAME, EXROM etc... They are ignored until software decides to enter C64 mode.

Ad 1: It's more or less the same as Ad 2 - it does not make much difference adding speeders or Burst mode. Perhaps with the possible exception that the SEQ line has to be added to some VHDL code, of cause.

Answer 6 · 2019-10-01T17:46:28.000Z

Ad 4: GideonZ/1541ultimate#31 (comment)
Thanks for sharing this, and would be good to get in contact with Xlar54 to compare note on this. As in my efforts on making the VDC work from the UII+ I run into similar issues. When checking the schematics it became apparent that within an C128 Issue 7 the R/W on the expansion port is not connected through to the VDC chip. So the VDC can only be switched from R/W by the CPU. The C128 Issue 6 had a different wiring and doesn't have this problem. That is why G. says a 'DMA hardware bug' in his comment. Well it is already good that Xlar54 confirms my findings as well and making VDC work would requires extra efforts. I will investigate further and this request can be closed for the moment.

Ad 3: Please read http://skoe.de/kernal/kernal-cartridge.pdf - there is nothing like that on the MMU for the kernal.
Thanks for sharing this as well. I have read it before but will look into this more closely to further understand. My quick scan learns that given the '/HiRam' isn't available on the expansion port they do some clever thinking to determine the state of this line. It looks similar as the trick to determining if I/O is active or RAM without having access to the CPU $01. Which also is possible using some clever reasoning. Surely, as the boot sequence of the C128 is different the GAME and EXROM are used in a different way. So I will look into this in a bit more detail and see if there is no indirect way to get to the right information to swap out the kernel. At least I see now what the thinking is and what it is that made it possible for the C64 side. So thanks sofar for this!

Ad 1: It's more or less the same as Ad 2 - it does not make much difference adding speeders or Burst mode. Perhaps with the possible exception that the SEQ line has to be added to some VHDL code, of cause.
Sorry, I fail to understand this comment. Do you mean perhaps that even if it would be possible to implement the burst mode you don't see the benefit of having this functionality implemented? Or do you mean something else entirely perhaps?

Answer 7 · 2019-10-01T17:53:14.000Z

I think extending 1581 support (with fastloaders) might result in burst mode support, too...

Answer 8 · 2020-06-02T10:20:29.000Z

regarding 3. AFAIK the documentation for Kernal replacement in the article by skoe is used in the EF3. This feature is not possible and even dangerous on the C128 according to some threads on Lemon and Forum64. AFAIR because of a missing feature/mode in the PLA of the C128.

Answer 9 · 2020-06-06T12:04:58.000Z

Hi J0Ju,

Thanks for commenting on this as well. I am drawing some inspiration from this article as well;

http://www.zimmers.net/anonftp/pub/cbm/documents/projects/memory/c128/kernal-switch.html

Surely it would require some changes besides just within the Ultimate2. But looking at the Art of the possible I wonder if it can be achieved. But for now I will conform to the statement it just cannot be done..

On a different note would you know how the burst mode and extended 1581 support is progressing as mentioned above as well? Or you are not involved in that perhaps?

Thanks and have a good day!