mattkretz/wg21-papers

improve "target/architecture" wording

Closed this issue · 2 comments

mattkretz commented
  • There's a comment in the synopsis that suggests to name the implementation-defined ABIs sse, avx, etc. Maybe that suggestion goes a little too far. Maybe no example names?
  • The terms "target", "architecture", "micro-architecture", "target architecture" need review & cleanup.
  • "most efficient data parallel execution for the element type T": The intent is to allow an implementation to choose a smaller vector width than the hardware is theoretically able to store in a vector register. (E.g. use SSE for int on SandyBridge where ymm registers can store int vectors, but operations are only available on xmm registers.)
mattkretz commented

On the 3rd point: After reviewing the AMD Zen architecture a bit, it seems "most efficient data parallel execution for the element type T" means 16-Byte vectors for Zen, even though the ISA supports AVX2. Ultimately, this is up to the implementation, but the intent of the wording is not to require the widest usable vector register size.

mattkretz commented

I added several margin notes with alternative text avoiding "target architecture" and "target system" in normative wording. Better?