mc68451

mc68451's Stars

• andreiw/ppc64le_hello

  ``Hello World'' for a Little-Endian OpenPower world (freestanding)

  Language:C184

• andreiw/prephv

  PReP emulation on Power8

  Language:C301

• NsCDE/NsCDE

  Modern and functional CDE desktop based on FVWM

  Language:CSS2k56

• orbcode/orbtrace

  Debug and parallel trace hardware for CORTEX-M (FPGA + support code)

  Language:Python13920

• alexforencich/verilog-axis

  Verilog AXI stream components for FPGA implementation

  Language:Python747229

• Wren6991/Hazard3

  3-stage RV32IMACZb* processor with debug

  Language:Verilog72450

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.3k699

• jgraph/drawio-desktop

  Official electron build of draw.io

  Language:JavaScript51.1k5k

• ecilasun/e32e

  Latest in the line of the E32 processors with better/generic cache placement

  Language:SystemVerilog102

• SpinalHDL/NaxRiscv

  Language:Scala26740

• trabucayre/openFPGALoader

  Universal utility for programming FPGA

  Language:C++1.2k264

• azonenberg/pcb-checklist

  Sign-off review checklist for PCB designs

  621102

• Manawyrm/ISASTM

  STM32-based ISA-over-USB-adapter

  Language:HTML1127

• MoonbaseOtago/vroom

  VRoom! RISC-V CPU

  Language:Verilog48122

• josephjkong/freebsd-device-drivers

  Code from the book "FreeBSD Device Drivers: A Guide for the Intrepid"

  Language:C112

• litex-hub/litex-boards

  LiteX boards files

  Language:Python380289

• thomasrussellmurphy/stx_cookbook

  Altera Advanced Synthesis Cookbook 11.0

  Language:Verilog9338

• defparam/PCI2Nano-RTL

  An open source FPGA PCI core & 8250-Compatible PCI UART core

  Language:Verilog405

• defparam/PCI2Nano-PCB

  An FPGA/PCI Device Reference Platform

  Language:Verilog283

• d953i/Custom_Part_Data_Files

  Xilinx PCIe to MIG DDR4 example designs and custom part data files

  Language:Tcl3519

• Nuand/bladeRF-wiphy

  bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

  Language:VHDL39650

• osafune/usjtag

  USB-Serial to Soft core JTAG I/O

  Language:Verilog22

• panda5mt/KyogenRV

  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

  Language:Scala445

• andysworkshop/stm32plus

  The C++ library for the STM32 F0, F100, F103, F107 and F4 microcontrollers

  Language:C++745224

• wfjm/wfjm.github.io

  wfjm home page

  Language:HTML41

• chipsalliance/Cores-VeeR-EH1

  VeeR EH1 core

  Language:SystemVerilog828220

• ultraembedded/biriscv

  32-bit Superscalar RISC-V CPU

  Language:Verilog869149

• enjoy-digital/fk33_hbm2_test

  HBM2 integration test on FK33 with LiteX

  Language:Python94

• openpower-cores/a2o

  Language:Verilog13825

• rxrbln/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog226