CHERI is not just for 64-bit architectures

[jrtc27]

The second paragraph of "Security analysis of CHERI ISA.pdf" says "These capabilities are 128-bit extensions of 64-bit pointers", but that is not true. CHERI as a model works with any address space size and any capability size greater than that (though you likely want a power-of-two if you want any hope of things working, and you need enough bits to have useful precision), and we have a 32-bit RISC-V version implemented. Please either generalise this accordingly or clarify that you are talking about specific instantiations of CHERI.