Pinned Repositories
8-3-Priority-encoder
A 4 to 2 priority encoder has 4 inputs : Y3, Y2, Y1 & Y0 and 2 outputs : A1 & A0. Here, the input, Y3 has the highest priority, whereas the input, Y0 has the lowest priority. In this case, even if more than one input is ‘1’ at the same time, the output will be the (binary) code corresponding to the input, which is having higher priority.
Automatic-washing-machine
This project proposes to demonstrate the capabilities and scope of Verilog HDL by implementing the control system of an automatic washing machine. The above mentioned objective by implementing the Control System of an automatic washing using the Finite State Machine model. The washing machine control system generates all the control signals required for the operation of washing machine and is designed using Verilog HDL.
Booths-multiplier
booth's multiplier defined by datapath and control path , where controller generates different control signals which are used by different modules to generate product
D-flipflop
The D flip-flop is an edge triggered device which transfers input data to Q on clock rising or falling edge.
DA-Based-LMS-Adaptive-filter
Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effectively used to implement FIR, IIR and FFT type.The DA logic replaces the MAC operation of convolution summation o into a bit-serial look-up table read and addition operation .
JK-Flipflop
The J-K flip-flop is the most versatile of the basic flip-flops. It has the input- following character of the clocked D flip-flop but has two inputs,traditionally labeled J and K. If J and K are different then the output Q takes the value of J at the next clock edge.If J and K are both low then no change occurs. If J and K are both high at the clock edge then the output will toggle from one state to the other. It can perform the functions of the set/reset flip-flop and has the advantage that there are no ambiguous states. It can also act as a T flip-flop to accomplish toggling action if J and K are tied together.
Router-1-x-3-
Router 1 x 3 verilog implementation
simple-MIPS32-processor
A pipelined implementation of MIPS32 processor using Verilog HDL MIPS32 is a Reduced Instruction Set Computer (RISC) architecture, and here, this particular processor is designed in Verilog HDL with 5 phases of pipeline, namely Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory (MEM), Write Back (WB). This design has a small subset of the instructions (and some simplifying assumptions), and verification of the design is done using some testbench and GTKWave simulator.
UART-protocol
UART - RTL Design and Verification
Universal-Shift-Register
Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift register along with parallel load provision is referred to as universal shift register.
mnmhdanas's Repositories
mnmhdanas/DA-Based-LMS-Adaptive-filter
Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effectively used to implement FIR, IIR and FFT type.The DA logic replaces the MAC operation of convolution summation o into a bit-serial look-up table read and addition operation .
mnmhdanas/Router-1-x-3-
Router 1 x 3 verilog implementation
mnmhdanas/UART-protocol
UART - RTL Design and Verification
mnmhdanas/Automatic-washing-machine
This project proposes to demonstrate the capabilities and scope of Verilog HDL by implementing the control system of an automatic washing machine. The above mentioned objective by implementing the Control System of an automatic washing using the Finite State Machine model. The washing machine control system generates all the control signals required for the operation of washing machine and is designed using Verilog HDL.
mnmhdanas/Booths-multiplier
booth's multiplier defined by datapath and control path , where controller generates different control signals which are used by different modules to generate product
mnmhdanas/Universal-Shift-Register
Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift register along with parallel load provision is referred to as universal shift register.
mnmhdanas/8-3-Priority-encoder
A 4 to 2 priority encoder has 4 inputs : Y3, Y2, Y1 & Y0 and 2 outputs : A1 & A0. Here, the input, Y3 has the highest priority, whereas the input, Y0 has the lowest priority. In this case, even if more than one input is ‘1’ at the same time, the output will be the (binary) code corresponding to the input, which is having higher priority.
mnmhdanas/D-flipflop
The D flip-flop is an edge triggered device which transfers input data to Q on clock rising or falling edge.
mnmhdanas/JK-Flipflop
The J-K flip-flop is the most versatile of the basic flip-flops. It has the input- following character of the clocked D flip-flop but has two inputs,traditionally labeled J and K. If J and K are different then the output Q takes the value of J at the next clock edge.If J and K are both low then no change occurs. If J and K are both high at the clock edge then the output will toggle from one state to the other. It can perform the functions of the set/reset flip-flop and has the advantage that there are no ambiguous states. It can also act as a T flip-flop to accomplish toggling action if J and K are tied together.
mnmhdanas/Parallel-IN-Parallel-OUT
In this type of register, there are no interconnections between the individual flip-flops since no serial shifting of the data is required. Data is given as input separately for each flip flop and in the same way, output also collected individually from each flip flop.
mnmhdanas/SPI-protocol
SPI is a synchronous, full duplex master-slave-based interface. The data from the master or the slave is synchronized on the rising or falling clock edge based on mode .Both master and slave can transmit data at the same time. The SPI interface got 4 wires.
mnmhdanas/Mod-N-Counter
Counters are sequential logic devices that follow a predetermined sequence of counting states triggered by an external clock (CLK) signal. Modulus Counters, or MOD counters, are defined based on the number of states that the counter will sequence before returning to its original value.
mnmhdanas/Parallel-Adder-subtractor
4 bit parallel adder/ subtractor circuit does both addition and subtraction by using 2 ripple carry adders and some xor gates
mnmhdanas/Parallel-IN-Serial-OUT
In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1. For every positive edge triggering of clock signal, the data shifts from one stage to the next. So, we will get the serial output from the right most D flip-flop.
mnmhdanas/RISC-V-rv32i
This is rv32i verilog design and it works fine for all instrcutions except lbu , lhu , ecall,ebreak
mnmhdanas/Serial-IN-Parallel-OUT
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is also called as serial input. For every positive edge triggering of clock signal, the data shifts from one stage to the next. In this case, we can access the outputs of each D flip-flop in parallel. So, we will get parallel outputs from this shift register.
mnmhdanas/Serial-IN-Serial-OUT
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is also called as serial input. For every positive edge triggering of clock signal, the data shifts from one stage to the next. So, we can receive the bits serially from the output of right most D flip-flop. Hence, this output is also called as serial output.
mnmhdanas/simple-MIPS32-processor
A pipelined implementation of MIPS32 processor using Verilog HDL MIPS32 is a Reduced Instruction Set Computer (RISC) architecture, and here, this particular processor is designed in Verilog HDL with 5 phases of pipeline, namely Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory (MEM), Write Back (WB). This design has a small subset of the instructions (and some simplifying assumptions), and verification of the design is done using some testbench and GTKWave simulator.
mnmhdanas/UP-DOWN-Counter
4 bit up down counter counts from 0000 to 1111 if control input is set HIGH ,else it would count from 1111 to 0000. it can be build by cascading 4 nos of D flipflops with a mux at the input node to choose between UP/DOWN