msaideroglu

Pinned Repositories

OpenFPGA
An Open-source FPGA IP Generator
Language:Verilog849 43 447163
Darknet-On-OpenCL
Darknet On OpenCL
Language:C++0 0 00
darknet_sowson
Darknet on OpenCL Convolutional Neural Networks on OpenCL on Intel & NVidia & AMD & Mali GPUs for macOS & GNU/Linux & Windows & FreeBSD
Language:C0 0 00
rv_core
This repo contains all SystemVerilog and ASIC Design stuff which is following my RISC-V Design Blog Series in LinkedIn.
Language:SystemVerilog00
SimpleList
SimpleList is a C++ program to refresh my C++ knowledge with VS-Code useful integrated tools (Git,Debug etc.) which is followed SavvyNik YT Channel.
Language:C++0 1 00
darknet
Darknet on OpenCL Convolutional Neural Networks on OpenCL on Intel & NVidia & AMD & Mali GPUs for macOS & GNU/Linux & Windows & FreeBSD
Language:C188 18 6632
ventus-gpgpu-verilog
GPGPU supporting RISCV-V, developed with verilog HDL
Language:Verilog71 3 812
vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Language:C++1k 67 1k395
skybox
Vortex Graphics
Language:Verilog63 4 412
vortex
Language:Verilog1.3k 38 128273

msaideroglu's Repositories

msaideroglu/Darknet-On-OpenCL
Darknet On OpenCL
Language:C++0 0 00
msaideroglu/darknet_sowson
Darknet on OpenCL Convolutional Neural Networks on OpenCL on Intel & NVidia & AMD & Mali GPUs for macOS & GNU/Linux & Windows & FreeBSD
Language:C0 0 00
msaideroglu/rv_core
This repo contains all SystemVerilog and ASIC Design stuff which is following my RISC-V Design Blog Series in LinkedIn.
Language:SystemVerilog00
msaideroglu/SimpleList
SimpleList is a C++ program to refresh my C++ knowledge with VS-Code useful integrated tools (Git,Debug etc.) which is followed SavvyNik YT Channel.
Language:C++0 1 00