Pinned Repositories
chisel-soc
dydra
fpga_designs
FPGA design repository
minimal-diplomacy
Example of Chisel3 Diplomacy
riscv-isadoc
riscv-vector-tests
Original test vector of RISC-V Vector Extension
support_ca_llvm_book
swimmer_riscv
Instruction set simulator for RISC-V
swimmer_rust
RISC-V Simulator written in Rust
xv6_translate
translation of XV6
msyksphinz-self's Repositories
msyksphinz-self/support_ca_llvm_book
msyksphinz-self/riscv-isadoc
msyksphinz-self/dydra
msyksphinz-self/fpga_designs
FPGA design repository
msyksphinz-self/riscv-vector-doc
msyksphinz-self/training
Exercise of Structure and Interpretation of Computer Programs
msyksphinz-self/fftw3
DO NOT CHECK OUT THESE FILES FROM GITHUB UNLESS YOU KNOW WHAT YOU ARE DOING. (See below.)
msyksphinz-self/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
msyksphinz-self/common_cells
Common SystemVerilog components
msyksphinz-self/fpnew
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
msyksphinz-self/litex
Build your hardware, easily!
msyksphinz-self/llvm-project
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.
msyksphinz-self/mcpat
An integrated power, area, and timing modeling framework for multicore and manycore architectures
msyksphinz-self/meno
Meno is a tool that visualizes hierarchical data, such as the sizes of directory trees or synthesized circuit sizes. It can be built into a single, standalone HTML file.
msyksphinz-self/NaxRiscv-Rtd
msyksphinz-self/ncnn
ncnn is a high-performance neural network inference framework optimized for the mobile platform
msyksphinz-self/pythondata-cpu-scariv
Scripts which automate the creation of the `litex.data` Python modules from various git repositories.
msyksphinz-self/riscv-bitmanip
Working draft of the proposed RISC-V Bitmanipulation extension
msyksphinz-self/riscv-bitmanip.github.io
msyksphinz-self/riscv-coremark
Setup scripts and files needed to compile CoreMark on RISC-V
msyksphinz-self/riscv-iommu-ja
msyksphinz-self/riscv-isa-sim
Spike, a RISC-V ISA Simulator
msyksphinz-self/riscv-meta
RISC-V Instruction Set Metadata
msyksphinz-self/riscv-tests
msyksphinz-self/riscv-vectorized-benchmark-suite
RiVEC Bencmark Suite
msyksphinz-self/rv8
RISC-V simulator for x86-64
msyksphinz-self/scariv_research
msyksphinz-self/sniper-docker-env
msyksphinz-self/snipersim
The Sniper Multi-Core Simulator
msyksphinz-self/uvm_study