nika100s

baller(real)

Pinned Repositories

cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Language:SystemVerilog00
devops_lesson_trial
Это репозиторий открытого урока по DevOPS Yodo.im
Language:CSS00
gneggnegi
main shiii bruh
00
quantization_noise_immunity
yep
Language:Python00
scr1_test
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Language:SystemVerilog00
vpn-kicker-tg-bot
just another tg bot lol
00

nika100s's Repositories

nika100s/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Language:SystemVerilog00
nika100s/devops_lesson_trial
Это репозиторий открытого урока по DevOPS Yodo.im
Language:CSS00
nika100s/gneggnegi
main shiii bruh
00
nika100s/quantization_noise_immunity
yep
Language:Python00
nika100s/scr1_test
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Language:SystemVerilog00
nika100s/vpn-kicker-tg-bot
just another tg bot lol
00