Does the clock matter and where can I change the clock freq of the bootloader?
Closed this issue · 10 comments
Is there a way to change the clock freq of the bootloader for the icebreaker bitsy?
The original design has a 12Mhz Clock built in, my custom design uses a 40Mhz Clock.
Does this influence the USB bootloader in any way?
Because when i plug it in my pc the power and cdone light goes on but when i hold the button and plug it in there isn't the usb detection sound and the device isn't found in the device manager :(
Hope u can help ._.
Yes, the clock has an influence.
USB needs 48 MHz and this is generated by the PLL from the input 12 MHz.
Unfortunately the iCE40 PLL can't generate 48 MHz from a 40 MHz input, there is just no ratio giving that frequency.
It might be possible to feed the input of the PLL with the SB_HFOSC setup to output 12 MHz, switching to a PLL_CORE instead of PLL_PAD ... never tried it in that config.
Alright thank you.
Why didn't u use the internal 48Mhz HFOSC for the bootloader, but instead used the PLL to create the 48Mhz clock?
Is this the right line if I delete the param CLKHF_DIV the HFOSC wouldn't get divided by four and it would use the 48Mhz internal osc directly or do I have to edit the USB clock anywhere else?
source: top.v in ice40-stub/rtl/
Thank u for your fast reply :)
The system needs both 24 MHz and 48 MHz hence why I recommend using the HFOSC to feed the PLL. Also the internal oscillator has a pretty high jitter which you can reduce by dividing and then using the PLL as a jitter cleaner.
By default it uses an external clock because the HFOSC spec is +- 10% variation which is WAY outside of the USB specs so ... might work, might not depending on external temperature, voltage, how well your particular chip was calibrated and how tolerant your PC is to clock offset ...
Ah gotcha!
I have already seen the jitter on the internal HFOSC so I won't give it a shot, but stick to the original design (12Mhz) and PLL my desired 40 Mhz Clock. Thank you for your help and for this wonderful repo. :)
Note that the icepll can't generate 40 MHz from a 12 MHz input either.
Your best bet if you want 40 MHz internally is to input 48 MHz directly (like the FOMU does).
Then from that you can derive 40 MHz for your design and ... well 48 MHz for USB obviously.
yes the icepll can't generate 40Mhz directly but can generate 120Mhz instead, which I can divide by 3 to get an 40Mhz out of an 12 Mhz Clock, right?
And obviously use a global clock buffer for the 40 Mhz.
You can't implement a divide by 3 in logic that would maintain a 50% duty cycle.
Also in general I'd recommend against generating clocks in logic unless you absolutely have to. Which here you don't you can just use a 48 M input.
This would also allow you to have both your 40M clock and a 48M clock at the same time to have USB running at the same time as your design.
Well if I would create a counter it wouldn't maintain a 50% duty cycle (?) where does that come from?
I understand that it is bad practice to generate a clock in logic, but I would have to edit the no2usb core (correct me if I am terribly wrong) and the top.v which I don't mind bc this is very complicated. I rather have a bad design than no design ._.
I have looked for alternatives and the tinyvga page mentions a 40Mhz clock freq for 60Hz, but as it is bad practice to do it my way i think I will go for an 49.5Mhz clock freq for 75Hz. I have used the icepll tool to insure the PLL can make a 49.5Mhz out of a 12 Mhz clock. Thank you for your effort and time u got me thinking in the right direction.
You don't need to modify anything in the core ... just in board.vh ( https://github.com/no2fpga/no2bootloader/blob/master/gateware/ice40/rtl/boards.vh )
you can for each supported board setup custom pll parameter.
In particular if your clock input is 48 MHz, you need :
`define PLL_DIVR 4'b0000
`define PLL_DIVF 7'b0001111
`define PLL_DIVQ 3'b100
`define PLL_FILTER_RANGE 3'b100
And for 800x600, pretty much all monitors will be happy with a 48 MHz pixel clock, just adapting the timings a bit.