nviennot/core-to-core-latency

[Result] Ampere Altra Q80-30, Neoverse-N1

zeroping opened this issue · 1 comments

I happen to have access to one of these, so here's the results.

There are some BIOS options for enabling NUMA support, so I tested in both monolithic mode and 2-node mode. Not all of the memory channels are populated in this system, so that might be affecting things too. I also attempted to run this with little other CPU activity and with the CPUs locked to the maximum 3 GHz. I'm happy to re-run with any suggestions to get cleaner data.

output-2-node.csv
output-no-numa.csv

# lscpu
Architecture:           aarch64
  CPU op-mode(s):       32-bit, 64-bit
  Byte Order:           Little Endian
CPU(s):                 80
  On-line CPU(s) list:  0-79
Vendor ID:              ARM
  BIOS Vendor ID:       Ampere(R)
  Model name:           Neoverse-N1
    BIOS Model name:    Ampere(R) Altra(R) Processor Q80-30 CPU @ 3.0GHz
    BIOS CPU family:    257
    Model:              1
    Thread(s) per core: 1
    Core(s) per socket: 80
    Socket(s):          1
    Stepping:           r3p1
    Frequency boost:    disabled
    CPU(s) scaling MHz: 35%
    CPU max MHz:        3000.0000
    CPU min MHz:        1000.0000
    BogoMIPS:           50.00
    Flags:              fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
Caches (sum of all):    
  L1d:                  5 MiB (80 instances)
  L1i:                  5 MiB (80 instances)
  L2:                   80 MiB (80 instances)
NUMA:                   
  NUMA node(s):         2
  NUMA node0 CPU(s):    0-39
  NUMA node1 CPU(s):    40-79
Vulnerabilities:        
  Itlb multihit:        Not affected
  L1tf:                 Not affected
  Mds:                  Not affected
  Meltdown:             Not affected
  Mmio stale data:      Not affected
  Retbleed:             Not affected
  Spec store bypass:    Mitigation; Speculative Store Bypass disabled via prctl
  Spectre v1:           Mitigation; __user pointer sanitization
  Spectre v2:           Mitigation; CSV2, BHB
  Srbds:                Not affected
  Tsx async abort:      Not affected