nviennot/core-to-core-latency

[Result] Elbrus-8C and Elbrus-8C2

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MCST Elbrus-8C, 8 cores, 1.2 GHz, elbrus-v4.csv, ~2014

Architecture:        e2k
Byte Order:          Little Endian
CPU(s):              32
On-line CPU(s) list: 0-31
Thread(s) per core:  1
Core(s) per socket:  8
Socket(s):           4
NUMA node(s):        4
Vendor ID:           E8C-SWTX
CPU family:          4
Model:               2
Model name:          E8C
CPU MHz:             1200
BogoMIPS:            2400.00
L1d cache:           64K
L1i cache:           128K
L2 cache:            512K
L3 cache:            16384K
NUMA node0 CPU(s):   0-7
NUMA node1 CPU(s):   8-15
NUMA node2 CPU(s):   16-23
NUMA node3 CPU(s):   24-31

MCST Elbrus-8C2, 8 cores, 1.55 GHz, elbrus-v5.csv, ~2018, engineering sample

Architecture:        e2k
Byte Order:          Little Endian
CPU(s):              8
On-line CPU(s) list: 0-7
Thread(s) per core:  1
Core(s) per socket:  8
Socket(s):           1
NUMA node(s):        1
Vendor ID:           Elbrus-MCST
CPU family:          5
Model:               2
Model name:          E8C2
CPU MHz:             1550
CPU max MHz:         1550.0000
CPU min MHz:         992.0000
BogoMIPS:            3100.00
L1d cache:           64K
L1i cache:           128K
L2 cache:            512K
L3 cache:            16384K
NUMA node0 CPU(s):   0-7