[BUG] SEMC_ConfigureDBI not setting REH2/REL2
Closed this issue · 3 comments
marcoosi commented
Describe the bug
According to i.MX RT1060X Processor Reference Manual, Rev. 1, 05/2022
, the DBICR1
register has 6 bits for REH and REL configuration. The SEMC_ConfigureDBI
function in fsl_semc.c
only writes the lower 4 bits.
To Reproduce
- Environment (please complete the following information):
- Tag/Commit hash: master
- Toolchain: any
- Board/SoC: IMXRT1062
- Steps to reproduce the behavior:
- Set
tRdxLow_Ns
in config struct to the value corresponding to 16 clock cycles of SEMC clock cycles will set the RDX Low Time to one clock cycle.
- Set
Expected behavior
Given that the IMXRT106x have 6 bits to configure the RDX Low and High Times, these should be taken into account.
Screenshots and console output
Additional context
mcuxcc commented
@marcoosi thank you for reporting the issue.
i have forward the issue to internal team, i will update to you if any feedback
zejiang0jason commented
marcoosi commented
@zejiang0jason the fix in #111 works for me.