nykwon000

Pinned Repositories

• Beginner-Physical-design

  This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.

  00

• breaking_cycles_in_noisy_hierarchies

  breaking cycles in noisy hierarchies

  Language:Python00

• cadence_power_switches

  cadence flow for genus and innovus with UPF added.

  Language:Tcl0000

• CIC2015_Verilog

  CIC競賽 cell-based design組 2015年考古題 simulation tool : NCVerilog synthesis tool : Design Compiler

  Language:Verilog0000

• cpu-internals

  Intel / AMD CPU Internals

  Language:C0000

• DAG

  Language:C++00

• digital-flow

  This is a tutorial on standard digital design flow

  Language:Tcl0000

• fedar-f1-rv64im

  5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

  Language:Verilog00

• graywolf

  Language:C0000

nykwon000's Repositories