Main analytical placer locks up for designs with high Distributed RAM usage.
chili-chips-ba opened this issue · 0 comments
chili-chips-ba commented
The exact same RTL+XDC went through both VTR (https://github.com/chipsalliance/f4pga) and Vivado w/o problem.
[https://symbioticeda.slack.com/archives/C053XV4R248/p1691005203874859]
See line#256 of [https://github.com/chili-chips-ba/openXC7-TetriSaraj/blob/main/1.hw/ip.cpu/picosoc_noflash.v], and change BRAM to DistRAM.
