simple TSC-CPU implementation
This is a repository presenting an implementation of a simple tsc-cpu.
Implementation versions are the followings:
-
Single Cycle CPU
-
Multi Cycle CPU
-
Pipelined CPU with Cache and DMA
This is a repository presenting an implementation of a simple tsc-cpu.
Implementation versions are the followings:
Single Cycle CPU
Multi Cycle CPU
Pipelined CPU with Cache and DMA