APCB configuration should support 1 TiB RAM
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There are a handful of configuration parameters that need to be set in the APCB to support the full 1 TiB of RAM on machines that have it. There is a 12 GiB region of physical address space immediately below 0x100_0000_0000 that is used in some very poorly specified manner by the IOMMU, possibly even if it's disabled. It is possible, at least sometimes, to remap the DRAM that would otherwise land in this region above that hole, just as is done for the normal MMIO hole below 4 GiB. The AMD AGESA manual explains the tokens that are involved and the limitations (which depend in turn on DRAM interleave settings). We should make sure that we're at least trying to do this remapping; if we also have to change interleave settings to make it work, we will need to do a performance evaluation to see whether it's better for the customer to lose 12 GiB of DRAM or use a suboptimal interleave.
I've moved this to MVP, as MVP+1 no longer makes sense given the decision to ship something nonviable.