[whymb] Missing writeback

[kalaider]

Before CPU0 can mark its cache line as "shared", the line must be written back to main memory to prevent data loss. It is worth mentioning here as long as we are concerned with main memory at all.

perfbook/appendix/whymb/whymemorybarriers.tex

Lines 792 to 796 in 1dd2b89

	\item CPU~0 receives the ``read'' message, and transmits the
	cache line containing the now-updated value of ``b''
	to CPU~1, also marking the line as ``shared'' in its own cache.
	\item CPU~1 receives the cache line containing ``b'' and installs
	it in its cache.

perfbook/appendix/whymb/whymemorybarriers.tex

Lines 892 to 898 in 1dd2b89

	\item CPU~0 receives the ``acknowledgement'' message, and puts
	the cache line containing ``b'' into the ``exclusive'' state.
	CPU~0 now stores the new value of ``b'' into the cache line.
	\item CPU~0 receives the ``read'' message, and transmits the
	cache line containing the new value of ``b''
	to CPU~1.
	It also marks its own copy of this cache line as ``shared''.

[paulmckrcu]

Good point, thank you!

This is addressed by commit e68dcb9 ("appendix/whymb: Add QQ on cachelines in dirty shared state") with your Reported-by.