Bug on FIFOs level width
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A bug was found on a project when using the psi_common_async_fifo (and it exist in the psi_common_async_fifo as well).
The bug is caused by a wrong width definition of the FIFOs level port (InLevel and OutLevel).
For most of the situations there is one extra bit in the port width taht is not necessary, and this is because the the port width is defined by log2ceil(Depth_g) downto 0.
I assume that the - 1 is missing to fit the situations where the FIFO depth is set to a power of 2, but it creates one extra bit in every other possible depth.
The proper way to set the port width would be log2ceil(Depth_g + 1) - 1 downto 0. In this way the port width will always have the minimum required bits to represent the configured depth.
I've fixed the issue and run the tests on a fork of the repo. It should be ready to be included in the main repo.
Branch with fix: https://github.com/0xF5A1/psi_common/tree/devel/fix-fifo-level-ports
Changes have been merge to develop branch - will soon be merge in master