Avoid bit-blasting in conversions

[leonardt]

import os, sys

import magma as m

 

mytype = m.Bits

 
class Test(m.Generator2):

    def __init__(self, x_len: int):

        self.io = m.IO(A=m.In(mytype[x_len]), B=m.In(mytype[x_len]), O=m.Out(mytype[x_len]))

 

        self.io.O @= self.io.A

        self.io.O[2] @=  self.io.B[1]

 

name = (__file__.split("/"))[-1]

name = (name.split("."))[0]

m.compile(f"build/{name}",Test(8),inline="True",disable_initial_blocks="True",output="mlir-verilog")

MLIR with bit-level representation:

hw.module @Test(%A: i8, %B: i8) -> (O: i8) {

    %0 = comb.extract %A from 0 : (i8) -> i1

    %1 = comb.extract %A from 1 : (i8) -> i1

    %2 = comb.extract %B from 1 : (i8) -> i1

    %3 = comb.extract %A from 3 : (i8) -> i1

    %4 = comb.extract %A from 4 : (i8) -> i1

    %5 = comb.extract %A from 5 : (i8) -> i1

    %6 = comb.extract %A from 6 : (i8) -> i1

    %7 = comb.extract %A from 7 : (i8) -> i1

    %8 = comb.concat %7, %6, %5, %4, %3, %2, %1, %0 : i1, i1, i1, i1, i1, i1, i1, i1

    hw.output %8 : i8

}

RTL with fields recovered by CIRCT:

// Generated by CIRCT unknown git version

module Test(     // <stdin>:1:1

  input  [7:0] A,

               B,

  output [7:0] O);

 

  assign O = {A[7:3], B[1], A[1:0]};               // <stdin>:4:10, :10:10, :11:5

endmodule