phanrahan/magma

Issues

• Circuit sublasses with arguments or verilog modules with parameters

  #1195 opened 2 years ago
  2

• How to improve the readability of generated verilog? Debug mode made no difference.

  #1193 opened 2 years ago
  2

• Interpretation of @m.inline_combinational() usage

  #1192 opened 2 years ago
  5

• CIRCT generates verilog files (*.v) with systemverilog features causing syntax issues with EDA tools

  #1191 opened 2 years ago
  2

• Support for custom interfaces

  #1190 opened 2 years ago
  4

• m.compile(..., output="verilog") leads to AttributeError: 'AnonRef' object has no attribute 'tuple'

  #1185 opened 2 years ago
  4

• [MLIR] How to add attribute and source location

  #1182 opened 2 years ago
  22

• [MLIR] Reset bug

  #1178 opened 2 years ago
  1

• [When] Register implicit enable logic with two contexts

  #1170 opened 2 years ago
  0

• [Circuit] Add interface to access underlying magma value of protocol type ports

  #1159 opened 2 years ago
  0

• [MLIR] Inline compile guarded module definitions

  #1143 opened 2 years ago
  0

• [Clock] Clock port is not automatically added to containing modules

  #1141 opened 2 years ago
  0

• [Types] Raise better error for non-existing Tuple key

  #1137 opened 2 years ago
  0

• [Primitives] Fix slice primitives

  #1135 opened 2 years ago
  2

• [InlineVerilog] Wire inlining produces bad Verilog when using `ifdef`

  #1133 opened 2 years ago
  2

• [When] Inferred latches incorrectly detected for array slices

  #1132 opened 2 years ago
  1

• [When] Mixing array bulk and elaborated wiring for arrays results in error

  #1125 opened 2 years ago
  0

• [MLIR] custom op 'comb.neg' is unknown

  #1123 opened 2 years ago
  2

• [Types] Add better error message for Bit/Bits equality operators with non-magma type

  #1119 opened 2 years ago
  0

• [Types] Add sext/zext for Bit types

  #1107 opened 2 years ago
  0

• [Types] Disallow empty product

  #1106 opened 2 years ago
  0

• [Array2] Array repr difference based on intermediate anon temp

  #1103 opened 2 years ago
  0

• [Types] Add fill (with 0 or 1) function for all types

  #1088 opened 2 years ago
  0

• [MLIR] Add support for module linking flow

  #1087 opened 2 years ago
  1

• [Types] Add support for get item syntax in tuple type

  #1086 opened 2 years ago
  0

• [Wiring] Combine unwire()/wire() into single rewire() function

  #1084 opened 2 years ago
  0

• [Wiring] Add rewire error mode

  #1082 opened 2 years ago
  0

• [Types] Add name argument for conversions

  #1081 opened 2 years ago
  0

• Support ReadyValid[None]

  #1079 opened 2 years ago
  1

• Revert #1072

  #1074 opened 2 years ago
  0

• Undriven port bug

  #1073 opened 2 years ago
  3

• Calling `m.bits` on a UInt should convert the value to Bits

  #1068 opened 2 years ago
  0

• Add getitem support on IO

  #1057 opened 3 years ago
  0

• Compiling to CoreIR changes the circuit representation

  #1035 opened 3 years ago
  3

• zext/sext should accept single bit

  #1031 opened 3 years ago
  0

• Implement right-hand-side operators for Bit (e.g. __ror__)

  #1030 opened 2 years ago
  0

• No module named 'magma.backend.mlir'

  #1021 opened 3 years ago
  0

• Recent changes broke garnet/mantle

  #1020 opened 3 years ago
  3

• Make `mux([.], s)` uniform for const `s` for Bit and Bits

  #1016 opened 3 years ago
  0

• Change `m.mux` type annotation+docs to accept `list` or `m.Array`

  #1009 opened 3 years ago
  1

• Unify math.py:* and bitutils.py:*

  #1007 opened 3 years ago
  0

• `concat` should return most specific type possible

  #1006 opened 3 years ago
  6

• repr hangs on combinatinal

  #995 opened 3 years ago
  1

• Error message for "closed" definition

  #993 opened 3 years ago
  0

• Magma Major Version Update: 3.0.0

  #985 opened 3 years ago
  0

• Consolidate conversion logic into type constructor

  #984 opened 3 years ago
  0

• @m.combinational2 got TypeError : unsupported operand type(s) for +: 'function' and 'list'

  #982 opened 3 years ago
  2

• Magma protocol losing type under ite

  #979 opened 3 years ago
  1

• Add logging/warning statements for auto clock wiring

  #977 opened 3 years ago
  1

• Improve handling of In(ReadyValid)

  #976 opened 3 years ago
  0