AXI-STREAM DMA start operation
ZGDIGE opened this issue · 4 comments
Hello, I am a little confused about the bare metal program：
1.CoreAXI4DMAController v2.0 provides two ways to start DMA operations, one is to use the startup register, and the other is to use the STRTDMAOP signal. I did not find a statement to configure the startup register in the bare metal program.
- Why does the operation of starting DMA in the bare metal program use the APB bus to generate the start signal instead of configuring the start register?
Hi ZGDIGE,
Thanks for your question!
The CoreAXI4DMAController Streaming Example demonstrates the CoreAXI4DMAController performing fabric-to-memory DMA stream transfers using its AXI4-Stream slave interface.
As such, in this example, the DMA controller does not initiate the DMA transfer itself instead, it is initiated by an AXI4-Steam master module, the AXI4_STREAM_DATA_GENERATOR.
To start an AXI4-Stream transfer from this module, you must write to it's start register which is accessible over the APB bus.
The CoreAXI4DMAController Block Transfer Example demonstrates the CoreAXI4DMAController performing memory-to-memory DMA block transfers using its AXI4 master DMA interface.
In this example, the DMA transfers are initiated from the CoreAXI4DMAController by writing to its start register.
For further information, please refer to the CoreAXI4DMAController Handbook and the CoreAXI4DMAController example projects.
Regards
Hello p-owens，
Thanks for your answer.
In the CoreAXI4DMAController Streaming Example, APB does not write the start signal directly to the DMA controller, but generates the TVALID signal. I read the handbook again. In 3.3.4, the DMA controller provides external start bits or start registers for internal descriptors. Because the stream descriptor is not an internal descriptor, there should be no need for external start bits and start registers. When the destination data ready bit is written, the bandwidth will be allocated by the DMA arbiter, which means that the stream transmission will be started at this time.
I don't know if I understand it correctly.
Regards
ZGDIGE,
When the START register of the AXI4_STREAM_DATA_GENERATOR module is written to, the module places valid data on TDATA and asserts TVALID to indicate to the slave (the CoreAXI4DMAController) that there is valid data present at the output.
The TVALID signal is part of the AXI4-Stream protocol signals, it is used in the handshake process between a master and a slave before an AXI4-Stream transfer can occur.
Regarding the destination data ready bit, see section 3.23 “Stream Descriptor Support”:
“The Destination Data Ready bit is used by control masters to denote when a buffer has been allocated for the reception of the stream data in the AXI4 memory-map address space.”
The CoreAXI4DMAController can accept stream transfer of up to 4KB before the Destination data ready bit is asserted.
In this case, the data would be cached in the internal stream cache.
The AXI4-Stream master initiates AXI4-Stream transfers, not the CoreAXI4DMAController.
Stream descriptors are fetched over the AXI4 DMA interface when TVALID is asserted for the first transfer in the AXI4-Stream transaction.
If part of a stream transaction has filled up the internal stream cache, no further transfers in the AXI4-Stream transaction will be acknowledged until the Destination Data Ready bit is asserted.
In this case, the CoreAXI4DMAController will use the AXI4-Stream flow control signalling mechanism and de-assert TREADY, stopping further stream transfers.
N.B.: There is no section 3.3.4 in the current (v2.1) of the CoreAXI4DMAController handbook.
Hope that clears it up for you.
Best
Hi p-owens，
Thank you for your patient answer, it gave me an enlightenment！
Best Wishes！