Add RISC-V Support
Closed this issue · 5 comments
Would love to have a crack at this one
Cool!
Just a warning: I have never used that core and I don't know anyone who has.
So this may be either frustrating to get to work or not produce very stable benchmarks or both.
Do you happen to have the hardware to try?
Maybe we use https://mou.sr/3vqVjIw? I could get some of those too.
I have the following:
Microcontroller: SiFive Freedom E310 (FE310-G002)
CPU: SiFive E31 CPU
Architecture: 32-bit RV32IMAC
Speed: 256 MHz (default), 320MHz (Max)
Performance: 1.61 DMIPs/MHz
Memory: 16 KB Instruction Cache, 16 KB Data Scratchpad
Other Features: Hardware Multiply/Divide, Debug Module, Flexible Clock Generation with on-chip oscillators and PLLs
I got liboqs running on QEMU's riscv_32 so I was feeling confident about getting this working but now I'm not so confident after your comment hahah
The ESP32-C3 is quite a bit cheaper than the SiFive board which is why I'd favor it. I was kind of hoping we can establish it as the standard benchmarking platform for 32-bit RISC-V (for crypto engineering papers).
But if you want to give it a try with the SiFive board first, then that'd also be okay for me. I have one somewhere as well.
Resolved by #50