hybrid vcpuid support

[haiwei-li]

Before hybrid architecture, some cpuids access in different cores will
represent different information. These cpuid leaves are per-cpu.

In hybrid architecture, there will be some other different information
of cpuids because of the different core types.

Even though these information in same type core are the same, we define
these cpu leaves as per-cpu for the sake of a unified implementation.

This patchset is introduced to filter out these cpuid list and expose
properly to vm.

The difference between P-core and E-core is like:

• 0x2. Cache and TLB Information.
• 0x4. Deterministic Cache Parameters.
• 0x6. Thermal and Power Management.
• 0xb. Extended Topology Enumeration.
• 0x14. Intel Processor Trace Enumeration.
• 0x16. Processor Frequency Information.
• 0x18. Deterministic Address Translation Parameters.
• 0x1a. Native Model ID Enumeration.
• 0x1c. Last Branch Records Information.
• 0x1f. V2 Extended Topology Enumeration.
• 0x80000006. Extended Cache Information.