PWM-Shift-Register
This project is based on the design of a Pulse Width Module (PWM) generator with an 8-bit shift register using Verilog HDL.
The modules for performing this project is as follows:
- PWM_Gen.v = Contains the verilog code for the main project, i.e the PWM shifting module.
- PWM_Test.v = Contains the verilog testbench code to simulate the project on Xilinx Vivado.
- ShiftReg.v = Contains the verilog code for the shift register module.