/PWM-Shift-Register

To design and implement an 8-bit shift register compatible with PWM Outputs using Verilog HDL

Primary LanguageVerilog

PWM-Shift-Register

This project is based on the design of a Pulse Width Module (PWM) generator with an 8-bit shift register using Verilog HDL.

The modules for performing this project is as follows:

  1. PWM_Gen.v = Contains the verilog code for the main project, i.e the PWM shifting module.
  2. PWM_Test.v = Contains the verilog testbench code to simulate the project on Xilinx Vivado.
  3. ShiftReg.v = Contains the verilog code for the shift register module.