Getting misaligned exception with 64 bit CPU
algrobman opened this issue · 3 comments
Hi,
I got misaligned load exception inside exception handler for ebreak tests.
it was in this code in arch_test.h
...
//
/ shared spcl int/excp dispatcher. /
/ JR to table in t3+t2, indexed by mcause /
//
spcl__MODE_()handler: // case table branch to special handler code, depending on mcause
LA( t3, clrint__MODE_()tbl)
// load spcl int/excpt handler dispatch table
add t3, t3, t2 // offset into the correct int/excpt dispatch table
slli t2, t5, 3 // index into 8b aligned dispatch entry and jump through it
add t3, t3, t2
LREG t3, 0(t3) <<<<<<<<<<<<<< this one got the exception
spcl__MODE_()dispatch:
jr t3 // this defaults to resto__MODE_()rtn
/**** this is the table of interrupt clearing routine pointers, which could include special handlers /
/ They default to RVMODEL macros above, which are model supplied, then jump to rtn code ****/
?????????? <<< missing .align ??????
clrint__MODE_()tbl: //this code should only touch t2..t6
#ifdef rvtest_vtrap_routine // M/S/V/U
.dword resto__MODE_()rtn // int cause 0 is reserved, error
.dword _MODE_()clr_Ssw_int // int cause 1 Smode SW int
.dword _MODE_()clr_Vsw_int // int cause 2 Vmode SW int
.dword _MODE_()clr_Msw_int // int cause 3 Mmode SW int
shouldn't the clrint__MODE()table have 8 bytes alignement enforcement with .align ?
Which version are you using? It's clearly an older one, and I think this was a bug that was fixed when the code was refactored to remove LA() macros.
The one in the repo has an .align 3 on line 1323.
yes, I used DB from ~3 months ago,
And BTW it works for me with LA() LA works if the target address is allocated not farer than 2GB from that instruction PC ..