riscv-non-isa/riscv-arch-test

FP floating point corner case isn't tested

allenjbaum opened this issue · 1 comments

allenjbaum commented

There is a strange corner case in FP arithmetic where a result can be normal, but the underflow flag is set.

This occurs for any result value that has exp=0 and mantissa 1.FFFFFF.000000 (through 1.FFFFF.7FFFFF ( I think).
When that result is rounded, ( depending on the rounding mode for the larger values), no rounding happens.
At this point, exponent is zero, so it's a denorm, and (IEEE and RV spec) underflow flag is set
But now the mantissa must be to be converted to a denorm.
The mantissa is shifted by one (so the "hidden bit is no longer hidden), and that shifts out the LSB - which is a "1"
Now it must round again, and adding back rounding bit (again depending on rounding mode) kicks the result back into normalized territory (the smallest normal number)

Multiply doesn't cover this case, and (because it was found in the wild) divide doesn't either.
I have no clue whether add, subtract, FMA, convert, or sqrt tests do, but I suspect not.

These test values must be added to all FP op test suites, single, double and half precision, for all rounding modes. (we don't need to test all possible sign variations, though)