riscv-non-isa/riscv-arch-test

Hypervisor Extension enable issue

Opened this issue · 5 comments

Our DUT hardware supports H extension, so we want to enable MISA.H = 1.
But Reference-sail_c_simulator doesn't support it at present, which causes some test cases to fail.
How to configure yaml files in this case?

Example in attach files:
Dubhe-90.zip

Test case fail cause analysis:
image
In function <Mxcpt_sig_sv> read misa to t1, Our DUT return misa=0x80000000001411AD, which cause branch unsatisfied.
But SAIL always return misa=0x800000000014112D, which doesn't match H extension.

The short answer is that Hypervisor has not been implemented in Sail yet, so you can't configure it.
The people who understand Sail and the people that understand the H-extension have a very small overlap.
There are some changes being made to the Sail model that should make implementation simpler... but not simple

what's your suggestion for next step? Can we just waive these test failures?

I have replaced SAIL with Spike and run test again. It looks all tests have passed.
And I have submitted the report to riscv-arch-test-reports (riscv-non-isa/riscv-arch-test-reports#6).
Would you please help to take a look?

Wow, I just reread my original comments, and its full of weird typos.
OK, I can merge this - but note that this didn't actually run any hypervisor tests!