Continued missing coverage for x0/non-x0 on registers (when all registers are the same)

[ssecatch-w]

This shows up in e/add-01.S
inst_4:
// rs1 == rs2 == rd, rs1==x0, rs2==x0, rd==x0, rs2_val == -268435457, rs1_val == 4
// opcode: add ; op1:x0; op2:x0; dest:x0; op1val:0x0; op2val:0x0
TEST_RR_OP(add, x0, x0, x0, 0, 0x0, 0x0, x10, 16, x11)

This is the only instantiation of rs1 == rs2 == rd, and with all the registers being x0, this doesn't check that an add is actually happening

In dataset.cgf, there is this:
rfmt_op_comb: &rfmt_op_comb
'rs1 == rs2 != rd': 0
'rs1 == rd != rs2': 0
'rs2 == rd != rs1': 0
'rs1 == rs2 == rd': 0
'rs1 != rs2 and rs1 != rd and rs2 != rd': 0

While this is similar to #306, it's another missing condition.
I can't tell if it's meant to be handled with the new code in riscv-software-src/riscv-ctg#79

However, I think all the coverage needs to have special conditions for "register is x0" vs "register is not x0", and there don't be to be the special x0 cases. I would think the defined coverage should replace all the lines with the x0 options.
For example:
'rs1 == rs2 != rd': 0
Would become:
'rs1 == rs2 != rd' and rs1 == 'x0' and rd != 'x0' : 0
'rs1 == rs2 != rd' and rs1 != 'x0' and rd == 'x0' : 0
'rs1 == rs2 != rd' and rs1 != 'x0' and rd != 'x0' : 0

and
'rs1 == rs2 == rd': 0
Would become:
'rs1 == rs2 == rd' and rs1 == 'x0' : 0
'rs1 == rs2 == rd' and rs1 != 'x0' : 0

#385 attempts to fix some of the missing x0 coverage, but I noticed that this case of rs1 == rs2 == rd == x0 is missing from the new code. As the ISA does allow for a 0 value for the divisor without throwing an exception, I believe this case is missing from div-01.S