mode bits inside "vector" entry in signature

[silabs-kjetil]

This issue was seen when using CLIC mode trap handler.

https://github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/env/arch_test.h#L1222

It looks like the signature should contain the trampoline table (mtvec) offset (excluding mode bits), however the code brings in all the bits from mtvec including bits 1:0 containing the mode. These mode bits which are 0b11 in the CLIC case will cause artifacts in the signature. It also looks like the vector offset signature is supposed to be placed at bits 15:6 so shifted 5 bits to the left, however the code only shifts 4 bits left.

This issue was also discussed in the following PR: #436 (comment)