riscv-non-isa/riscv-arch-test

misalign-jal-01.S without support for compressed instruction signature mismatch

Opened this issue · 5 comments

ArbnorSh commented

The reference model used is Sail, and only the second line of the signature output is different from the DUT.
How to find what is causing this mismatch? All other tests in privilege directory are passing (same signature with ref).

$ diff 
< 56ff747d
---
> d6ff74dd

ref.signature.txt
DUT.signature.txt
misalign-jal-01.log.txt

allenjbaum commented

I've been trying to see what is going on. I don't know if the log is the DUT or SAIL, but what is being store in the signature is the delta between the address of the beginning of the test, and a pseudo-random value in a register. The problem seems to be that Sail and the DUT have different values as starting addresses.
This sounds like a test bug, frankly, but I can't be sure unless I can see the other log. I'm a little puzzled that this hasn't turned up earlier, and that is what really odd.

ArbnorSh commented

@allenjbaum
The log is SAIL, the DUT does not have such mechanism implemented as SAIL that dumps all the verbose info to a log file.
The issue seems to be this instruction (from ref) address 0x800004E4 - sub a0,a0,sp, I can confirm that a0 here has the same value in DUT and in SAIL, that value is 0x56FF76DD, but sp differs. And yes you're right, the DUT has instructions located in ROM that start from address 0 and data in RAM that start from address 0x80000000.
I am attaching the disassemble for DUT and REF.
ref_disass.txt
dut_disass.txt

allenjbaum commented
ArbnorSh commented

All implementations I am seeing in github, run these tests with Compressed instruction support. Note in this case DUT does not implement the C extension and Sail is being run with -C or --disable-compressed. If you have any DUT reference, please share that and I can check this test there!

allenjbaum commented