Unexpected Zfh's fdiv test appear when no Zfh enable

When using the latest main branch with RISCOF with ISA RV32IMFZicsr, the Zfh/src/fdiv_bx-01.S tests (where x denotes every fdiv tests in Zfh) appeared in the test unexpectedly.

With some comparison between other tests in Zfh, I'm not fully sure but suspicious that the regex in check ISA is wrong, where originally be:

riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b1-01.S

Line 32 in 8a0cdce

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b1)

While in others like regex in mul is:

riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmul_b1-01.S

Line 32 in 8a0cdce

    
           RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmul_b1)

It seems to be a similar problem as #448

I tried to reproduce this problem using sail, with the following config: sail_isa.yaml

Seems could be fixed with some simple changes, shall I make a pr for it if it's a problem?

Yes, please. Every Zfh test should require Zfh! (not just mul and div), though they seem to be the only ones that don't (besides Flh.align, which doesn't seem to even require F in the RVTEST_CASE, though it does in the RVTEST_ISA), which doesn't make sense unless it is unless used for FinX)

Fixed via #454

454 has been mreged, so closing this one